Published by A.Asenov, Semiwise.  24.01.20  

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Abstract: In this White Paper we present a detailed simulation study of the novel Flat Field Transistor (FFT) aiming to improve the performance, lower the leakage and reduce the statistical variability in 20nm and earlier bulk CMOS technology generations. In this device the implanted Source/Drain extensions and deep p-n junctions are replaced by epitaxially overgrown Source/Drain regions rising above the channel interface leading to superior electrostatic integrity.

 

The FFT performance is highlighted in comparison with typical 20 nm bulk CMOS technology

transistors. First, results illustrating the transistor performance improvement are presented. This is followed by a detailed study of the transistor variability and reliability. The corresponding improvement in the circuit performance is illustrated using ring oscillator (RO) and 6-T SRAM simulations.

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